Professional

I joined Intel Corporation in Santa Clara, California in 1986 and have worked there ever since. I was a member of the architecture and design teams for six microprocessors: the 486, Pentium, Pentium II, Itanium, Knight's Ferry, and Knight's Corner. I worked on microarchitectural techniques for energy-efficient chip multiprocessors in Intel's Microprocessor Research Labs. I'm currently working on the design of future throughput processors.

I presented a talk on RTL Design on a Laptop at the 18th Annual Electronic Design Process Symposium in Monterey, California in April 2011.

• RTL Design on a Laptop. EDPS 2011.

I presented a short talk on Energy per Instruction as part of an Intel video series for software developers.

• Energy per Instruction. Intel Software Network Video, February 2008.

I was the General Chair for the IEEE International Conference on Computer Design (ICCD) 2005, which was held right here in San Jose. Here is a link to the ICCD website.

• ICCD Home Page

I hold 64 issued United States patents as of December 2011.

Publications

Here is a list of my external publications.

• Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan. Larrabee: A Many-Core x86 Architecture for Visual Computing. ACM Transactions on Graphics, Volume 27, Issue 3, August 2008.
  
  
• Murali Annavaram, Ed Grochowski, Paul Reed. Implications of Device Timing Variability on Full Chip Timing. Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture, HPCA 2007.
  
  
• Ed Grochowski, Murali Annavaram. Energy per Instruction Trends in Intel Microprocessors. Technology@Intel Magazine, March 2006.
  
  
• Murali Annavaram, Ed Grochowski, John Shen. Fixing the Sequential Bottleneck by Regulating Energy Per Instruction on CMPs. Technology@Intel Magazine, October 2005.
  
  
• Murali Annavaram, Ed Grochowski, John Shen. Mitigating Amdahl's Law through EPI Throttling. Proceedings of the 32nd Annual International Symposium on Computer Architecture, ISCA 2005.
  
  
• Ed Grochowski, Ronny Ronen, John Shen, Hong Wang. Best of Both Latency and Throughput. Proceedings of the 22nd IEEE International Conference on Computer Design, ICCD 2004.
  
  
• Ed Grochowski, David Ayers, Vivek Tiwari. Microarchitectural di/dt Control. IEEE Design & Test of Computers, May/June 2003.
  
  
• Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Shen. Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. Proceedings of the 8th International Symposium on High Performance Computer Architecture, HPCA 2002.
  
  
• Ed Grochowski, David Ayers, Vivek Tiwari. Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. Proceedings of the 8th International Symposium on High Performance Computer Architecture, HPCA 2002.
  
  
• Ryan Rakvic, Ed Grochowski, Bryan Black, Murali Annavaram, Trung Diep, John Shen. Performance Advantage of the Register Stack in Intel Itanium Processors. Proceedings of the 2nd Workshop on Explicitly Parallel Instruction Computing Architecture and Compilers, EPIC-2, 2002.
  
  
• Ed Grochowski, Ken Shoemaker. Issues in the Implementation of the i486 Cache and Bus. Proceedings of the 7th IEEE International Conference on Computer Design, ICCD 1989, pages 193-198.